The MC10E/100E452 is a 5-bit differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V The fully differential design of the device makes it ideal for very high frequency applications where a registered data path is necessary. pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V may also rebias AC coupled inputs. When used, decouple V via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V The 100 Series contains temperature compensation.
Features
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Differential D, CLK and Q; VBB Reference Available
1100MHz Min. Toggle Frequency
Asynchronous Master Reset
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors, Output Q3bar will Default to LowState When Inputs Are Left Open
ESD Protection: > 1 kV HBM, > 75 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
