The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW.The 100 Series contains temperature compensation.
Features
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1100MHz Min. Toggle Frequency
Differential Outputs
Asynchronous Master Reset
Dual Clocks
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 kV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
