The LPC3180 is an ARM9-based microcontroller for embedded applications requiring high performance combined with low power dissipation. It achieves these objectives through the combination of NXP®"s state-of-the-art 90 nanometer technology with an ARM926EJ-S CPU core with a Vector Floating Point (VFP) coprocessor and a large array of standard peripherals including USB On-The-Go.
The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per ARM Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard architecture with separate 32 kB instruction and data caches, a demand paged MMU, DSP instruction extensions with a single cycle MAC, and Jazelle Java bytecode execution hardware. A block diagram of the microcontroller is shown .
Power optimization in this microcontroller is done through process and technology development (Intrinsic Power), and architectural means (Managed Power).
The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0 full-speed interface, seven UARTs, two I²C-bus interfaces, two SPI ports, a Secure Digital (SD) interface, and a 10-bit ADC in addition to many other features.
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## Features
**Key features**
* ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, running at up to 208 MHz.
* 64 kB of SRAM.
* High-performance multi-layer AHB bus system provides a separate bus for CPU data and instruction fetch, two data buses for the DMA controller, and another for the USB controller.
* External memory interfaces: one supports DDR and SDR SDRAM, another supports single-level and multi-level NAND flash devices and can serve as an 8-bit parallel interface.
* General purpose DMA controller that can be used with the SD card and SPI interfaces, as well as for memory-to-memory transfers.
* USB 2.0 full-speed device, host (OHCI compliant), and OTG block. A dedicated PLL provides the 48 MHz USB clock.
* Multiple serial interfaces, including seven UARTs, two SPI controllers, and two single master I²C-bus interfaces.
* SD memory card interface.
* Up to 55 GPI, GPO, and GPIO pins. Includes 12 GPI pins, 24 GPO pins, and six GPIO pins.
* 10-bit ADC with input multiplexing from three pins.
* Real-Time Clock (RTC) with separate power supply and power domain, clocked by a dedicated 32 kHz oscillator. Includes a 128 byte scratch pad memory. The RTC may remain active when the rest of the chip is not powered.
* 32-bit general purpose high-speed timer with 16-bit pre-scaler with capture and compare capability.
* 32-bit millisecond timer driven from the RTC clock. Interrupts may be generated using two match registers.
* Watchdog timer.
* Two PWM blocks with an output rate up to 50 kHz.
* Keyboard scanner function provides automatic scanning of up to an 8 x 8 key matrix.
* Standard ARM test/debug interface for compatibility with existing tools.
* Emulation trace buffer with 2 k x 24-bit RAM allows trace via JTAG.
* On-chip crystal oscillator.
* Stop mode saves power, while allowing many peripheral functions to restart CPU activity.
* On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal.
