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LPC1830FET256 库存 & 价格

LPC1830FET256
显示的图像仅供参考,应从产品数据表中获得准确的规格。
LPC1830FET256 NXP
NXP
  • 制造商:
    NXP
  • 制造商型号#:
    LPC1830FET256
  • 百芯编号#:
    CM625966762
  • 价格(CNY):
  • 百芯库存:
    225
  • 可供应量:
    142 个在库
    此为供应商库存,需要与销售确认
  • 产品描述:
    MCU 32Bit LPC1800 ARM Cortex M3 RISC ROMLess 2.5V/3.3V 256Pin LBGA
  • 文档: 符合 RoHS 标准 3D模型
LPC1830FET256 购买 LPC1830FET256 库存和价格更新于 2024-05-31 03:50:22
  • 刷新
    器件型号: LPC1830FET256
    百芯编号: CM625966762
    制造商: NXP
    价格
    总计: 367
    MOQ: 1
    库存地点: 香港
    发货日期: 2024/06/05 (预期 )
  • 购买
    *由于库存数量、价格不断波动,请 联系我们 获取型号最新价格和库存。

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    LPC1830FET256 规格 显示相似产品 (99+)
    类型
    描述
    选择
    制造商
    NXP
    引脚数
    256 Pin
    3D模型
     3D模型
    封装
    LBGA-256
    位数
    32 Bit
    显示相似产品
    LPC1830FET256 数据规格书
    LPC1830FET256 数据手册Datasheet
    153 Pages, 2776 KB
    2014/06/11
    查看
    LPC1830FET256 产品设计参考
    1284 Pages, 9401 KB
    2017/07/26
    查看
    LPC1830FET256 其它数据手册Datasheet
    157 Pages, 2789 KB
    查看
    尺寸 & 包装
    类型
    描述
    产品生命周期
    Unknown
    符合标准
    类型
    描述
    RoHS标准
    RoHS Compliant
    产品概述
    • Overview
    • The LPC1830FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2.0 Host/OTG/Device and CAN 2.0B. Operating at speeds up to 180 MHz, the LPC1830 also features two new configurable peripherals: a SPI Flash Interface and a State Configurable Timer. All members of the series include a Wakeup Interrupt Controller allowing automatic wake from any priority interrupt as well as four reduced power modes: Sleep, Deep-Sleep, Power-Down, and Deep Power-Down.
    • MoreLess
    • ## Features
    • * ARM Cortex-M3 processor, running at frequencies of up to 180 MHz
    • * ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions
    • * ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
    • * Non-maskable Interrupt (NMI) input
    • * JTAG and Serial Wire Debug
    • * ETM and ETB support
    • * System tick timer
    • * 200 kB SRAM for code and data use
    • * 32 kB ROM containing boot code and on-chip software drivers
    • * Crystal oscillator with an operating range of 1 MHz to 25 MHz
    • * 12 MHz internal RC oscillator trimmed to 1 % accuracy
    • * Ultra-low power RTC crystal oscillator
    • * Clock output
    • * Two PLLs allow CPU operation up to the maximum CPU rate
    • * Quad SPI Flash Interface with four lanes and data rates of up to 40 MB/s
    • * 10/100T Ethernet MAC with RMII and MII interfaces and DMA support
    • * One High-speed USB 2.0 Host/Device/OTG interface with DMA
    • * One High-speed USB 2.0 Host/Device interface with DMA support
    • * Four 550 UARTs with DMA support: one UART with full modem interface
    • * One UART with IrDA interface
    • * One C_CAN 2.0B controller with one channel
    • * Two SSP controllers with FIFO and multi-protocol support
    • * One Fast-mode Plus I2C-bus interface with monitor mode
    • * One standard I2C-bus interface with monitor mode and standard I/O pins
    • * One I2S interface with DMA support and with one input and one output
    • * External Memory Controller (EMC)
    • * SD/MMC card interface
    • * Eight-channel General-Purpose DMA (GPDMA) controller
    • * Up to 164 General-Purpose Input/Output (GPIO) pins
    • * GPIO registers are located on the AHB for fast access
    • * State Configurable Timer (SCT) subsystem on AHB
    • * Four general-purpose timer/counters with capture and match capabilities
    • * One motor control PWM for three-phase motor control
    • * One Quadrature Encoder Interface (QEI)
    • * Repetitive Interrupt timer (RI timer)
    • * Windowed watchdog timer
    • * Ultra-low power Real-Time Clock (RTC) on separate power domain
    • * Alarm timer; can be battery powered
    • * One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s
    • * Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s
    • * Hardware-based AES security engine programmable through an on-chip API
    • * Two 128-bit secure OTP memories for AES key storage and customer use
    • * Unique ID for each device
    • * Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip voltage regulator
    • * RTC power domain can be powered separately by a 3 V battery supply
    • * Four reduced power modes
    • * Overdrive mode to increase CPU and bus clock frequency
    • * Processor wake-up from Sleep mode via wake-up interrupts
    • * Wake-up from Deep-sleep, Power-down, and Deep power-down modes
    • * Brownout detect with four separate thresholds for interrupt and forced reset
    • * Power-On Reset (POR)
    • ## Target Applications
    • * Industrial
    • * Consumer
    • * White goods
    • * RFID readers
    • * e-Metering
    • ## Features

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