NXP’s exclusive software-driven I/O Handler (IOH) on the LPC11E37HFBD64 gives designers the ultimate design flexibility to adapt the MCU configuration and functionality to fit application needs at any time during the design cycle. The I/O Handler is a software-driven block supported by software libraries that can be used to add performance, connectivity and flexibility to system designs. The I/O Handler can emulate serial interfaces such as UART, I²C, or I²S with no or very low additional CPU load and can off-load the CPU by performing processing-intensive functions like DMA transfers in hardware.
Software libraries available for the I/O Handler include I²S, I²C, UART, CRC, threshold ADC conversion, and DMA functionality. The libraries can be downloaded at: www.lpcware.com/ioh
It’s easy to get started with the I/O Handler:
1\. Download the free library file for the function you need at www.lpcware.com/ioh
2\. Install (on IOH hardware block)
3\. Run application
4\. It’s that easy! (For the full instruction set on using the IOH libraries, go to www.lpcware.com/ioh
So whether it’s deciding on communication interfaces, accommodating late design changes, or requiring more performance or power efficiency from the application, the I/O Handler gives designers the ability to save time and cost while adding functionality to meet design deadlines.
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## Features
* System:
* ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
* ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
* Non Maskable Interrupt (NMI) input selectable from several input sources.
* System tick timer.
* Memory:
* Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase (256 byte) access.
* 4 kB on-chip EEPROM data memory; byte erasable and byte programmable; on-chip API support.
* 12 kB SRAM data memory.
* 16 kB boot ROM.
* In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.
* ROM-based 32-bit integer division routines.
* Debug options:
* Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).
* Serial Wire Debug.
* Digital peripherals:
* Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.
* Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
* Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.
* High-current source output driver (20 mA) on one pin.
* High-current sink driver (20 mA) on true open-drain pins.
* Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs.
* Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO).
* Analog peripherals:
* 10-bit ADC with input multiplexing among eight pins.
* Serial interfaces:
* USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3).
* Two SSP controllers with FIFO and multi-protocol capabilities.
* I²C-bus interface supporting the full I²C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
* Software-enabled IO-handler for hardware emulation of serial interfaces and DMA. (LPC11E37HFBD64/401 only.)
* Clock generation:
* Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
* 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock.
* Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output.
* PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.
* Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.
* Power control:
* Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes.
* Power profiles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call.
* Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
* Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, or the watchdog interrupt.
* Processor wake-up from Deep power-down mode using one special function pin.
* Power-On Reset (POR).
* Brownout detect with four separate thresholds for interrupt and forced reset.
* Unique device serial number for identification.
* Single 3.3 V power supply (1.8 V to 3.6 V).
* Temperature range -40 °C to +85 °C.
* Available as LQFP64, LQFP48, and HVQFN33 packages.
