* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * Auto Power-down during deselect * Double cycle deselect * Snooze MODE for reduced-power standby * JTAG Boundary Scan for PBGA package * Power Supply: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% * JEDEC 100-Pin TQFP package * Lead-free available
