The CD74HCT193E is a 4-bit high speed CMOS presettable synchronous Binary Up/Down Counter with asynchronous reset. Presetting the counter to the number on the preset data inputs (P0 to P3) is accomplished by a low asynchronous parallel load input (PL\\). The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count and returns to high at the maximum count.
Two outputs for n-bit cascading
Look-ahead carry for high-speed counting
Balanced propagation delay and transition times
Significant power reduction compared to LSTTL logic ICs
