The CD4026BE is a CMOS Decade Counter/Divider with decoded 7-segment display outputs and display enable. The CD4026B consists of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. Inputs common to both types are CLOCK, RESET & CLOCK INHIBIT, common outputs are CARRY OUT and the seven decoded outputs. Additional inputs and outputs for the counter include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "C-SEGMENT" outputs. A high RESET signal clears the decade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. The CLOCK INHIBIT signal can be used as a negative-edge clock if the clock line is held high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence.
