The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width communications applications.
The ADS58C48 uses third-generation _SNRBoost3G_ technology to overcome SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the _SNRBoost3G_ technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate _SNRBoost3G_ coefficients can be programmed for each channel.
The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset.
The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400Mbps at 200 MSPS sample rate) makes it possible to use low-cost FPGA-based receivers. The strength of the LVDS output buffers can be increased to support 50 ohms differential termination. This allows the output clock signal to be connected to two separate receiver chips with an effective 50 termination (such as the two clock ports of the GC5330).
The same digital output pins can also be configured as a parallel 1.8V CMOS interface.
It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The device is specified over the industrial temperature range (–40°C to 85°C).
Maximum Sample Rate: 200 MSPS
High Dynamic Performance
SFDR 82 dBc at 140 MHz
72.3 dBFS SNR in 60 MHz BW Using _SNRBoost3G_ technology
