The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE#) is LOW. When OE# is HIGH, the bus output is in a high impedance state. The LVTH373 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal latches are designed for low-voltage (3.3V) V applications, but with the capability to provide a TTL interface to a 5V environment. The LVT373 and LVTH373 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
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Input and output interface capability to systems at 5V VCC
Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free bus loading
Outputs source/sink -32 mA/+64 mA
Functionally compatible with the 74 series 373
ESD performance:Human-body model > 2000VMachine model > 200VCharged-device model > 1000V
