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数据手册 > LED,驱动器 > TI > TLC5940RHBR 数据手册PDF > TLC5940RHBR 用户编程手册 第 1/2 页
TLC5940RHBR
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TLC5940RHBR 用户编程手册 - TI

  • 制造商:
    TI
  • 分类:
    LED,驱动器
  • 封装
    VQFN-32
  • 描述:
    16Channel LED Driver w/EEprom DOT Correction & Grayscale PWM Control 32-VQFN -40℃ to 85℃
更新时间: 2025-05-13 17:13:17 (UTC+8)

TLC5940RHBR 用户编程手册

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Start
Set Dot Correction Input
(VPRG = High)
DC Input Cycle
Counter > n*96 -1
Reset Counter = 0
YES
NO
Pulse XLAT
Set SIN to DC
Data[Counter]
Pulse SCLK
Increment Counter
(Counter = Counter +1)
n = Number of
TLC5940 in series
Counter = index
variable for DC Data
Set DCPRG = High
Change DC
Data?
LOD Check
Reset Data_Counter = 0
Is
Data_Counter
> n*192-1
YES
NO
Set SIN to 1
Pulse SCLK
Increment
Data_Counter
(Data_Counter =
Data_Counter + 1)
Set XLAT = High
Set BLANK = Low
Pulse GSCLK
Wait > 2 micro Seconds
Set XLAT = Low
Set BLANK = High
After LOD Check Function the Status
Information Data packet is available in the
TLC5940 Shift Register. It may be read
from the SOUT pin (of the last device in
series) during the following GS input cycle.
Grayscale Data input cycle
Combined with Grayscale PWM
cycle
Reset GSCLK_Counter = 0
Is GSCLK_Counter
> 4095
YES
NO
Set BLANK = Low
(Turn LED’s On)
Reset Data_Counter = 0
Set SIN to GS
Data[Data_Counter]
Pulse SCLK
Increment
Data_Counter
(Data_Counter =
Data_Counter + 1)
Pulse GSCLK
Increment
GSCLK_Counter
(GSCLK_Counter =
GSCLK_Counter + 1)
Is
Data_Counter
> n*192-1
YES
NO
Set BLANK = High
Is VPRG = High
nf
f
CYCLEPWM
SCLK
×
×=
192
11
_
SCLKCYCLEPWM
ff
n
1
192
11
_
××=
f
SCLK
= minimum serial
data frequency
f
PWM_CYCLE
= frequency of
complete Grayscale cycle
n = number of TLC5940
in series
Set VPRG = Low
Set FirstCycleFlag = 1
Is FirstCycleFlag =
1
Pulse XLAT to latch in
GS data
Pulse SCLK
Set FirstCycleFlag = 0
FirstCycleFlag is set to high for first GS cycle after DC input cycle to add one
additional SCLK pulse
Data_Counter = index variable for GS Data
GSCLK_Counter = GS PWM Pulse Counter
n = number of TLC5940 in series
Check LOD
Function?
No
Yes
Set GSCLK = Low
Set SCLK = Low
Set DCPRG = Low
Set VPRG = High
Set XLAT = Low
Set BLANK = High
Data input must be complete before GSCLK_Counter reaches 4096.
Use the following equations to verify that the data input cycle will be
completed before the PWM cycle is completed.
TLC5940 Programing Flow Chart v0.1
9/29/05
No
Yes
Use DC EEPROM
data
YES
NO
Set DCPRG = Low
Save DC data to
EEPROM?
Set DCPRG = Low
Set VPRG = 22
Volts
Pulse DCPRG
Set VPRG = High
YES
NO
YES
NO

TLC5940RHBR 数据手册 PDF

TLC5940RHBR 数据手册
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38 页, 1356 KB
TLC5940RHBR 产品设计参考
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18 页, 1281 KB
TLC5940RHBR 用户编程手册
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TLC5940RHBR 其它数据手册
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