Rev. 1.5 10/11 Copyright © 2011 by Silicon Laboratories Si3050 + Si3011/18/19
Si3050+Si3011/18/19
PROGRAMMABLE VOICE DAA SOLUTIONS
Features
Applications
Description
The Si3050+Si3011/18/19 Voice DAA chipset provides a highly-programmable
and globally-compliant foreign exchange office (FXO) analog interface. The
solution implements Silicon Laboratories' patented isolation capacitor technology,
which eliminates the need for costly isolation transformers, relays, or
opto-isolators, while providing superior surge immunity for robust field
performance. The Voice DAA is available as a chipset, a system-side device
(Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in
a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin
TSSOP, a 16-pin SOIC, or a 20-pin QFN and requires minimal external
components. The Si3050 interfaces directly to standard telephony PCM
interfaces.
Functional Block Diagram
PCM highway data interface
µ-law/A-law companding
SPI control interface
GCI interface
80 dB dynamic range TX/RX
Line voltage monitor
Loop current monitor
+6 dBm or +3.2 dBm TX/RX level
mode
Parallel handset detection
3 µA on-hook line monitor current
Overload detection
Programmable line interface
AC termination
DC termination
Ring detect threshold
Ringer impedance
TIP/RING polarity detection
Integrated codec and 2- to 4-wire
analog hybrid
Programmable digital hybrid for
near-end echo reduction
Polarity reversal detection
Programmable digital gain in 0.1 dB
increments
Integrated ring detector
Type I and II caller ID support
Pulse dialing support
3.3 V power supply
Daisy-chaining for up to 16 devices
Greater than 5000 V isolation
Patented isolation technology
Ground start and loop start support
Available in Pb-free RoHS-compliant
packages
DSL IADs
VoIP gateways
PBX and IP-PBX systems
Voice mail systems
DECT base stations
Hybrid, AC
and DC
Terminations
Ring Detect
Off-Hook
IB
SC
DCT
VREG2
DCT2
DCT3
RNG1
RNG2
QB
QE
QE2
RX
Si3018/19
VREG
Si3050
Control
Data
Interface
Isolation
Interface
CS
SCLK
SDI
SDO
SDI THRU
Control
Logic
PCLK
DTX
DRX
FSYNC
Line
Data
Interface
RG
TGD
TGDE
RESET
AOUT/INT
RGDT
Isolation
Interface
US Patent# 5,870,046
US Patent# 6,061,009
Ordering Information
See page 106.
Package Options
Si3050
Si3011/18/19
GND
RESET
C2A
C1A
VA
VDD
GND
15
14
13
17
18
16
AOUT/INT
RG
NC
NC
TGD
TGDE
10
11
12
8
7
9
CS
FSYNC
PCKLK
DTX
DRX
RGDT
4
5
6
2
1
3
SCLK
SDITHR
NC
NC
SDO
SDI
22
23
24
20
19
21
Si3050
Top View
IGND
PAD
1
QE
RNG2
DCT3
QB
QE2
C2B
NC
C1B
IGND
RNG1
SC
RX
IB
DCT2
NC
DCT
IGND
VREG2
VREG
NC
2
5
4
3
6
15
12
13
14
7 1098
11
17181920 16
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