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DS21Q352
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DS21Q352 用户编程手册 - Maxim Integrated

  • 制造商:
    Maxim Integrated
  • 分类:
    接口,芯片
  • 封装
    BGA-256
  • 描述:
    Quad T1/E1 Transceiver (3.3V,5V)
更新时间: 2025-05-11 14:04:46 (UTC+8)

DS21Q352 用户编程手册

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Maxim > Design Support > Technical Documents > Application Notes > T/E Carrier and Packetized > APP 461
Keywords: framer, SCT, single chip transceiver, AT&T, TR54016, ANSI, T1.403, FDL, facility data link,
PRM, performance report message, ESF
APPLICATION NOTE 461
Programming and Controlling the FDL on
DS2141A, DS2151
May 11, 2001
Abstract: This application note describes how to use the legacy facility data link (FDL) controller found in
all Dallas Semiconductor T1 framers and single chip transceivers (SCTs). The FDL is used in T1
communications to pass data and information outside of the normal communications signal. This allows
information such as line performance monitoring data or maintenance information to be gathered and
passed along without interfering with the normal operation of the T1 line. Because of the complexity of
the FDL specifications, special data and status registers were added to the T1 devices which allow the
designer to take advantage of the FDL functionality. The application note goes into an in-depth
explanation of how the legacy FDL circuitry operates and explains the different protocols used to carry
information through the FDL. To assist in the software design, flow charts are included with step-by-step
instructions for transmitting and receiving data over the FDL. In the end, the designer should have
enough information to implement the necessary FDL communications in the target system.
Introduction
This application note shows how to program and control the facility data link (FDL) on the DS2141A and
DS2151. The ANSI T1.403 and AT&T TR54016 protocols used within receive and transmit FDL have
been summarized.
Because of expected future changes in FDL requirements, the DS2141A and DS2151 T1 controller
makes use of software in the host to support the communications that occur on the FDL. Using the
host's software to help control the FDL allows designs to be easily modified as the standards progress.
The DS2141A and DS2151 implement in hardware the more basic functions of controlling the FDL, such
as byte aligning to the FDL data stream. In current T1 networks there are two common protocols that
exist on the FDL in the extended superframe (ESF) framing mode. One is defined in the American
National Standards Institute (ANSI) document T1.403-1989 and the other is defined in the AT&T
publication TR54016. Depending on the carrier used, either one (or both) of these protocols may be
required. This application note details how a host would interface with the DS2141A and DS2151 to
extract information from the FDL and insert data into the FDL. The user has the option on the DS2141A
and DS2151 to either use its on-board RFDL and TFDL registers or to use the RLINK and TLINK pins to
extract/insert data from/into the FDL data stream. This application note covers the usage of the RFDL
and TFDL registers. The specifics of the two FDL protocols are not fully covered. (Note: All references to
specific data values are in hexadecimal, which is denoted by the value enclosed within < >.) Please refer
to the two ANSI documents mentioned for more details.
Page 1 of 6

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