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CY7B991V
3.3 V RoboClock
®
Low Voltage
Programmable Skew Clock Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-07141 Rev. *L Revised November 2, 2016
3.3 V RoboClock
®
Low Voltage Programmable Skew Clock Buffer
Features
■ All output pair skew <100 ps typical (250 ps max)
■ 3.75 MHz to 80 MHz output operation
■ User-selectable output functions:
❐ Selectable skew up to 18 ns
❐ Inverted and non-inverted
❐ Operation at one-half and one-quarter input frequency
❐ Operation at 2 × and 4 × input frequency (input as low as
3.75 MHz)
■ Zero input to output delay
■ 50% duty cycle outputs
■ Low-voltage transistor-transistor logic (LVTTL) outputs drive
50 terminated lines
■ Operates from a single 3.3 V supply
■ Low operating current
■ 32-pin plastic leaded chip carrier (PLCC) package
■ Low cycle-to-cycle jitter (100 ps typical)
Functional Description
The CY7B991V 3.3 V RoboClock
®
low-voltage programmable
skew clock buffer (LVPSCB) offers user-selectable control over
system clock functions. These multiple output clock drivers
provide the system integrator with functions necessary to
optimize the timing of high-performance computer systems.
Each of the eight individual drivers – arranged in four pairs of
user controllable outputs – can drive terminated transmission
lines with impedances as low as 50 . This delivers minimal
output skews and full-swing logic levels (LVTTL).
Each output is hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are determined
by the operating frequency, with outputs able to skew up to ±6
time units from their nominal ‘zero’ skew position. The
completely-integrated phase-locked loop (PLL) allows external
load and transmission line delay effects to be canceled. When
this ‘zero delay’ capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This feature minimizes clock
distribution difficulty, allowing maximum system clock speed and
flexibility.
For a complete list of related resources, click here.
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
Logic Block Diagram
