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TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880C –DECEMBER 2013–REVISED JANUARY 2015
TMS320F2837xD Dual-Core Delfino™ Microcontrollers
1 Device Overview
1.1 Features
1
• Dual-Core Architecture • Analog Subsystem
– Two TMS320C28x 32-Bit CPUs – Four Dual-Mode Analog-to-Digital Converters
(ADCs)
– 200 MHz
• 16-Bit Mode
– IEEE 754 Single-Precision Floating-Point
– 1.1 MSPS Each (up to 4.4-MSPS
– Trigonometric Math Unit (TMU)
System)
– Viterbi/Complex Math Unit (VCU-II)
– Differential
• Two Programmable Control Law Accelerators
– Up to 12 External Channels
– 200 MHz
• 12-Bit Mode
– IEEE 754 Single-Precision Floating-Point
– 3.5 MSPS Each (up to 14-MSPS System)
Executes Code Independently of Main CPU
– Single-Ended
• On-Chip Memory
– Up to 24 External Channels
– 512KB or 1MB of Flash (ECC-Protected)
• Single Sample-and-Hold (S/H) on Each ADC
– 172KB or 204KB of RAM (ECC or Parity)
• HW Integrated Post-Processing of ADC
– Dual-Zone Security Supporting Third-Party
Conversions
Development
– Saturating Offset Calibration
• Clock and System Control
– Error From Setpoint Calculation
– Two Internal Zero-Pin 10-MHz Oscillators
– High, Low, and Zero-Crossing Compare,
– On-Chip Crystal Oscillator and External Clock
With Interrupt Capability
Input
– Trigger-to-Sample Delay Capture
– Windowed Watchdog Timer Module
– Eight Windowed Comparators With 12-Bit DAC
– Missing Clock Detection Circuitry
References
• 1.2-V Core, 3.3-V I/O Design
– Three 12-Bit Buffered DAC Outputs
• System Peripherals
• Enhanced Control Peripherals
– Two External Memory Interfaces (EMIFs) With
– 24 Pulse Width Modulator (PWM) Channels
ASRAM and SDRAM Support
With Enhanced Features
– Dual 6-Channel Direct Memory Access (DMA)
– 16 High-Resolution Pulse Width Modulator
Controller
(HRPWM) Channels
– Up to 169 Individually Programmable,
• High Resolution on Both A and B Channels
Multiplexed General-Purpose Input/Output
of 8 PWM Modules
(GPIO) Pins With Input Filtering
• Dead-Band Support (on Both Standard and
– HW Interrupt Controller
High Resolution)
– Multiple Low-Power Mode Support With External
– Six Enhanced Capture (eCAP) Modules
Wakeup
– Three Enhanced Quadrature Encoder Pulse
– JTAG Emulation Connection
(eQEP) Modules
• Communications Peripherals
– 8 Sigma-Delta Filter Module (SDFM) Input
– USB 2.0 (MAC + PHY)
Channels, 2 Parallel Filters per Channel
– Two CAN-Bus Ports (Pin-Bootable)
• Standard SDFM Data Filtering
– Three High-Speed (40-MHz) SPI Ports
• Comparator Filter for Fast Action for Out of
(Pin-Bootable)
Range
– Two Multichannel Buffered Serial Ports
– Four Serial Communications Interfaces (SCIs)
(Pin-Bootable)
– Two I
2
C Interfaces (Pin-Bootable)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
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