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TMS320DM647
TMS320DM648
www.ti.com
SPRS372H –MAY 2007–REVISED APRIL 2012
TMS320DM647/TMS320DM648 Digital Media Processor
Check for Samples: TMS320DM647, TMS320DM648
1 Features
1
• High-Performance Digital Media Processor • C64x+ L1/L2 Memory Architecture
– 720-MHz, 800-MHz, 900-MHz, 1.1-GHz – 256K-bit (32K-byte) L1P Program RAM/Cache
C64x+™ Clock Rates [Direct Mapped]
– 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900), – 256K-bit (32K-byte) L1D Data RAM/Cache
0.91 ns (-1100) Instruction Cycle Time [2-Way Set-Associative]
– 5760, 6400, 7200, 8800 MIPS – 2M-bit/256K-byte (DM647) or 4M-Bit/512K-
byte) (DM648) L2 Unified Mapped
– Eight 32-Bit C64x+ Instructions/Cycle
RAM/Cache [Flexible Allocation]
– Fully Software-Compatible With C64x/Debug
– Commercial Temperature Ranges (-720, -900,
• Supports Little Endian Mode Only
and -1100 only)
• Five Configurable Video Ports
– Extended Temperature Ranges (-800 only)
– Providing a Glueless I/F to Common Video
– Industrial Temperature Ranges (-720, -900,
Decoder and Encoder Devices
and -1100 only)
– Supports Multiple Resolutions/Video
• VelociTI.2™ Extensions to VelociTI™
Standards
Advanced Very-Long-Instruction-Word (VLIW)
• VCXO Interpolated Control Port (VIC)
TMS320C64x+™ DSP Core
– Supports Audio/Video Synchronization
– Eight Highly Independent Functional Units
• External Memory Interfaces (EMIFs)
With VelociTI.2 Extensions:
– 32-Bit DDR2 SDRAM Memory Controller With
• Six ALUs (32-/40-Bit), Each Supports
512M-Byte Address Space (1.8-V I/O)
Single 32-bit, Dual 16-bit, or Quad 8-bit
– Asynchronous 16-Bit Wide EMIF (EMIFA)
Arithmetic per Clock Cycle
• Up to 128M-Byte Total Address Reach
• Two Multipliers Support Four 16 x 16-bit
• 64M-Byte Address Reach per CE Space
Multiplies (32-bit Results) per Clock Cycle
– Glueless Interface to Asynchronous
or Eight 8 x 8-bit Multiplies (16-Bit
Memories (SRAM, Flash, and EEPROM)
Results) per Clock Cycle
– Synchronous Memories (SBSRAM and ZBT
– Load-Store Architecture With Non-Aligned
SRAM)
Support
– Supports Interface to Standard Sync Devices
– 64 32-bit General-Purpose Registers
and Custom Logic (FPGA, CPLD, ASICs,
– Instruction Packing Reduces Code Size
etc.)
– All Instructions Conditional
• Enhanced Direct-Memory-Access (EDMA)
– Additional C64x+™ Enhancements
Controller (64 Independent Channels)
• Protected Mode Operation
• 3-Port Gigabit Ethernet Switch Subsystem
• Exceptions Support for Error Detection
• Four 64-Bit General-Purpose Timers (Each
and Program Redirection
Configurable as Two 32-Bit Timers)
• Hardware Support for Modulo Loop Auto-
• One UART (With RTS and CTS Flow Control)
Focus Module Operation
• One 4-wire Serial Port Interface (SPI) With Two
• C64x+ Instruction Set Features
Chip-Selects
– Byte-Addressable (8-/16-/32-/64-bit Data)
• Master/Slave Inter-Integrated Circuit (I2C
– 8-bit Overflow Protection
Bus™)
– Bit-Field Extract, Set, Clear
• Multichannel Audio Serial Port (McASP)
– Normalization, Saturation, Bit-Counting
– Ten Serializers and SPDIF (DIT) Mode
– VelociTI.2 Increased Orthogonality
• 16/32-Bit Host-Port Interface (HPI)
– C64x+ Extensions
• Advanced Event Triggering (AET) Compatible
• Compact 16-bit Instructions
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
• Additional Instructions to Support
Interconnect (PCI) Master/Slave Interface
Complex Multiplies
Conforms to PCI Specification 2.3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2007–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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