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TMS320DM6441
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SPRS359E–SEPTEMBER 2006–REVISED AUGUST 2010
TMS320DM6441
Digital Media System-on-Chip
Check for Samples: TMS320DM6441
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture
– C64x+™ DSP Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
• 405-MHz (Max) at 1.05 V or 513-MHz (Max)
at 1.2 V – 80K-Byte L1D Data RAM/Cache (2-Way
Set-Associative)
– ARM926EJ-S™ Clock Rate
– 64K-Byte L2 Unified Mapped RAM/Cache
• 202.5-MHz (Max) at 1.05 V or 256-MHz
(Flexible RAM/Cache Allocation)
(Max) at 1.2 V
• ARM926EJ-S Core
– Eight 32-Bit C64x+ Instructions/Cycle
– Support for 32-Bit and 16-Bit (Thumb®
– 4752 C64x+ MIPS
Mode) Instruction Sets
– Fully Software-Compatible With C64x /
– DSP Instruction Extensions and Single Cycle
ARM9™
MAC
• Advanced Very-Long-Instruction-Word (VLIW)
– ARM® Jazelle® Technology
TMS320C64x+™ DSP Core
– Embedded ICE-RT™ Logic for Real-Time
– Eight Highly Independent Functional Units
Debug
• Six ALUs (32-/40-Bit), Each Supports
• ARM9 Memory Architecture
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle – 16K-Byte Instruction Cache
• Two Multipliers Support Four 16 x 16-Bit – 8K-Byte Data Cache
Multiplies (32-Bit Results) per Clock
– 16K-Byte RAM
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
– 8K-Byte ROM
Results) per Clock Cycle
• Embedded Trace Buffer™ (ETB11™) With 4KB
– Load-Store Architecture With Non-Aligned
Memory for ARM9 Debug
Support
• Endianness: Little Endian for ARM and DSP
– 64 32-Bit General-Purpose Registers
• Video Imaging Co-Processor (VICP)
– Instruction Packing Reduces Code Size
• Video Processing Subsystem
– All Instructions Conditional
– Front End Provides:
– Additional C64x+™ Enhancements
• CCD and CMOS Imager Interface
• Protected Mode Operation
• BT.601/BT.656 Digital YCbCr 4:2:2
• Exceptions Support for Error Detection
(8-/16-Bit) Interface
and Program Redirection
• Preview Engine for Real-Time Image
• Hardware Support for Modulo Loop
Processing
Operation
• Glueless Interface to Common Video
• C64x+ Instruction Set Features
Decoders
– Byte-Addressable (8-/16-/32-/64-Bit Data)
• Histogram Module
– 8-Bit Overflow Protection
• Auto-Exposure, Auto-White Balance, and
– Bit-Field Extract, Set, Clear
Auto-Focus Module
– Normalization, Saturation, Bit-Counting
• Resize Engine
– Compact 16-Bit Instructions
– Resize Images From 1/4x to 4x
– Additional Instructions to Support Complex
– Separate Horizontal/Vertical Control
Multiplies
1
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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