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TMS320C82
DIGITAL SIGNAL PROCESSOR
SPRS048 — APRIL 1998
1
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
Copyright © 1998 Texas Instruments Incorporated
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251-1443
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Single Chip Parallel MIMD DSP
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Over 1.5 Billion RISC-like Operations per
Second
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Master Processor (MP)
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32-Bit RISC Processor
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IEEE-754 Floating Point
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4K-Byte Instruction Cache
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4K-Byte Data Cache
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Two Parallel Processors (PPs)
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32-Bit Advanced DSP Processors
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64-Bit Opcode Provides Many
Parallel Operations per Cycle
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4K-Byte Instruction Cache, 4K-Byte
Parameter RAM, and 8K Bytes of Data
RAM per PP
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Transfer Controller (TC)
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64-Bit Data Transfers
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Up to 480M-Byte/s Transfer Rate
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32-Bit Addressing
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Direct EDO DRAM/VRAM Interface
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Direct SDRAM Interface
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Dynamic Bus Sizing
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Intelligent Queuing and Cycle
Prioritization
GGP PACKAGE
(BOTTOM VIEW)
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Big or Little Endian Operation
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44K Bytes of On-Chip RAM
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4G-Byte Address Space
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16.6 ns Cycle Time
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3.3-V Operation
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IEEE 1149.1 Test Port (JTAG)
description
The TMS320C82 is a single chip, MIMD (multiple instruction/multiple data) parallel processor capable of
performing over 1.5 billion operations per second. It consists of a 32-bit RISC Master Processor with a
120-MFlop IEEE Floating Point Unit, two 32-bit parallel-processing DSPs (PPs), and a Transfer Controller
with up to 480 Mbyte/sec transfer rate. All the processors are tightly coupled via an on-chip crossbar which
provides shared access to on-chip RAM. This performance and programmability make the ‘C82 ideally
suited for video, imaging, and high-speed telecommunication applications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet
.
