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TMS320DM6467
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SPRS403H –DECEMBER 2007–REVISED JUNE 2012
TMS320DM6467
Digital Media System-on-Chip
Check for Samples: TMS320DM6467
1 Digital Media System-on-Chip (DMSoC)
1.1 Features
12
• High-Performance Digital Media SoC • C64x+ L1/L2 Memory Architecture
– 594-, 729-MHz C64x+™ Clock Rate – 32K-Byte L1P Program RAM/Cache (Direct
Mapped)
– 297-, 364.5-MHz ARM926EJ-S™ Clock Rate
– 32K-Byte L1D Data RAM/Cache (2-Way Set-
– Eight 32-Bit C64x+ Instructions/Cycle
Associative)
– 4752, 5832 C64x+ MIPS
– 128K-Byte L2 Unified Mapped RAM/Cache
– Fully Software-Compatible With
(Flexible RAM/Cache Allocation)
C64x/ARM9™
• ARM926EJ-S Core
– Supports SmartReflex™ [-594 only]
– Support for 32-Bit and 16-Bit (Thumb®
• Class 0
Mode) Instruction Sets
• 1.05-V and 1.2-V Adaptive Core Voltage
– DSP Instruction Extensions and Single Cycle
– Extended Temp Available [-594 only]
MAC
– Industrial Temp Available [-729 only]
– ARM® Jazelle® Technology
• Advanced Very-Long-Instruction-Word (VLIW)
– EmbeddedICE-RT™ Logic for Real-Time
TMS320C64x+™ DSP Core
Debug
– Eight Highly Independent Functional Units
• ARM9 Memory Architecture
• Six ALUs (32-/40-Bit), Each Supports
– 16K-Byte Instruction Cache
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
– 8K-Byte Data Cache
Arithmetic per Clock Cycle
– 32K-Byte RAM
• Two Multipliers Support Four 16 x 16-Bit
– 8K-Byte ROM
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • Embedded Trace Buffer™ (ETB11™) With 4KB
Results) per Clock Cycle Memory for ARM9 Debug
– Load-Store Architecture With Non-Aligned • Endianness: Little Endian for ARM and DSP
Support
• Dual Programmable High-Definition Video
– 64 32-Bit General-Purpose Registers Image Co-Processor (HDVICP) Engines
– Instruction Packing Reduces Code Size – Supports a Range of Encode, Decode, and
Transcode Operations
– All Instructions Conditional
• H.264, MPEG2, VC1, MPEG4 SP/ASP
– Additional C64x+™ Enhancements
• 99-/108-MHz Video Port Interface (VPIF)
• Protected Mode Operation
– Two 8-Bit SD (BT.656), Single 16-Bit HD
• Exceptions Support for Error Detection
(BT.1120), or Single Raw (8-/10-/12-Bit) Video
and Program Redirection
Capture Channels
• Hardware Support for Modulo Loop
– Two 8-Bit SD (BT.656) or Single 16-Bit HD
Operation
(BT.1120) Video Display Channels
• C64x+ Instruction Set Features
• Video Data Conversion Engine (VDCE)
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Horizontal and Vertical Downscaling
– 8-Bit Overflow Protection
– Chroma Conversion (4:2:2↔4:2:0)
– Bit-Field Extract, Set, Clear
• Two Transport Stream Interface (TSIF) Modules
– Normalization, Saturation, Bit-Counting
(One Parallel/Serial and One Serial Only)
– Compact 16-Bit Instructions
– TSIF for MPEG Transport Stream
– Additional Instructions to Support Complex
– Simultaneous Synchronous or
Multiplies
Asynchronous Input/Output Streams
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2007–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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