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P2020NXN2KFC 产品设计参考 - NXP

  • 制造商:
    NXP
  • 分类:
    微处理器
  • 封装
    PBGA-689
  • 描述:
    MPU QorIQ RISC 32Bit 1000MHz 1.5V/1.8V/2.5V/3.3V 689Pin TEPBGA II Tray
更新时间: 2022/08/10 11:41:52 (UTC+8)

P2020NXN2KFC 产品设计参考

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Freescale Semiconductor
Application Note
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Preliminary—Subject to Change Without Notice
This application note provides information to programmers
so that they may write optimal code for the PowerPC™ e500
embedded microprocessor cores. The target audience
includes performance-oriented writers of both compilers and
hand-coded assembly.
1 Overview
The e500 core implements the Book E version of the
PowerPC architecture. In addition, the e500 core adheres to
the Freescale Book E implementation standards (EIS). These
standards were developed to ensure consistency among
Freescale’s Book E implementations.
This document may be regarded as a companion to The
PowerPC™ Compiler Writers Guide (CWG) with major
updates specific to the e500 core. This document is not
intended as a guide for making a basic PowerPC compiler
work. For basic compiler guidelines, see the CWG. However,
many of the code sequences suggested in the CWG are not
optimal for the e500 core.
The following documentation provides information about
the e500 core as well as some more general information
about Book E architecture:
PowerPC™ e500 Core Complex Reference Manual
(functional description)
EREF: A Reference for Freescale Book E and the
e500 Core (programming model). The EREF
AN2665
Rev. 0, 04/2005
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. e500 Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. e500 Core Microarchitecture . . . . . . . . . . . . . . . . . . 13
4. Pipeline Rule Overview . . . . . . . . . . . . . . . . . . . . . . 15
5. Fetch Stage Considerations . . . . . . . . . . . . . . . . . . . . 16
6. Decode Considerations . . . . . . . . . . . . . . . . . . . . . . . 31
7. Issue Queue Considerations . . . . . . . . . . . . . . . . . . . 33
8. Execute Stage Considerations . . . . . . . . . . . . . . . . . . 34
9. Completion Stage Considerations . . . . . . . . . . . . . . . 39
10. Write Back Stage Considerations . . . . . . . . . . . . . . . 41
11. Instruction Attributes . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Application of Microarchitecture to Optimal Code . 48
13. Branch Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
14. General Instruction Choice and Scheduling . . . . . . . 55
15. SPE-Specific Optimizations . . . . . . . . . . . . . . . . . . . 56
16. Load/Store-Specific Optimizations . . . . . . . . . . . . . . 58
17. SPE Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
18. Optimized Code Sequences . . . . . . . . . . . . . . . . . . . 71
19. Improvements by Compilers . . . . . . . . . . . . . . . . . . . 77
20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Appendix A. e500 Rule Summary . . . . . . . . . . . . . . . . . . . .79
e500 Software Optimization Guide (eSOG)

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