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DM385, DM388
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SPRS821D –MARCH 2013–REVISED DECEMBER 2013
DM385 and DM388 DaVinci™ Digital Media Processor
Check for Samples: DM385, DM388
1 High-Performance System-on-Chip (SoC)
1.1 Features
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• High-Performance DaVinci Digital Media • Programmable High-Definition Video Image
Processors Coprocessing (HDVICP v2) Engine
– Up to 1000-MHz ARM® Cortex™-A8 RISC – Encode, Decode, Transcode Operations
Processor
– H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4
– Up to 2000 ARM Cortex-A8 MIPS SP/ASP, JPEG/MJPEG
• ARM Cortex-A8 Core – Fourth-Generation Motion-Compensated
Noise Filter (DM388 Only)
– ARMv7 Architecture
• Media Controller
• In-Order, Dual-Issue, Superscalar
Processor Core – Controls the HDVPSS, HDVICP2, and ISS
• NEON™ Multimedia Architecture • Endianness
• Supports Integer and Floating Point – ARM Instructions and Data – Little Endian
• Jazelle® RCT Execution Environment • HD Video Processing Subsystem (HDVPSS)
• ARM Cortex-A8 Memory Architecture – Two 165-MHz HD Video Capture Inputs
– 32KB of Instruction and Data Caches • One 16- or 24-Bit Input, Splittable Into
Dual 8-Bit SD Capture Ports
– 256KB of L2 Cache with ECC
• One 8-, 16-, or 24-Bit HD Input and 8-Bit
– 64KB of RAM, 48KB of Boot ROM
SD Input Capture Port
• 256KB of On-Chip Memory Controller (OCMC)
– Two 165-MHz HD Video Display Outputs
RAM
• One 16-, 24-, or 30-Bit and One 16- or 24-
• Imaging Subsystem (ISS)
Bit Output
– Camera Sensor Connection
– Component HD Analog Output
• Parallel Connection for Raw (up to 16-Bit)
– Composite Analog Output
and BT.656/BT.1120 (8- or 16-Bit)
– Digital HDMI 1.3 Transmitter with Integrated
• CSI2 Serial Connection
PHY
– Image Sensor Interface (ISIF) for Handling
– Advanced Video Processing Features Such
Image and Video Data From the Camera
as Scan, Format, and Rate Conversion
Sensor
– Three Graphics Layers and Compositors
– Image Pipe Interface (IPIPEIF) for Image and
Video Data Connection Between Camera • 32-Bit DDR2, DDR3, and DDR3L SDRAM
Sensor, ISIF, IPIPE, and DRAM Interface
– Image Pipe (IPIPE) for Real-Time Image and – Supports up to 400 MHz for DDR2, 533 MHz
Video Processing for DDR3, and 533 MHz for DDR3L
– Resizer – Up to Two x 16 Devices, 2GB of Total
Address Space
• Resizing Image and Video From 1/16x to
8x – Dynamic Memory Manager (DMM)
• Generating Two Different Resizing • Programmable Multi-Zone Memory
Outputs Concurrently Mapping
• Hardware 3A Engine (H3A) for Generating • Enables Efficient 2D Block Accesses
Key Statistics for 3A (AE, AWB, and AF)
• Supports Tiled Objects in 0°, 90°, 180°, or
Control
270° Orientation and Mirroring
• Face Detect (FD) Engine
– Hardware Face Detection for up to 35 Faces
Per Frame
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Device/BIOS, XDS are trademarks of Texas Instruments.
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PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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