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User's Guide
SCAU027B–March 2009–Revised March 2011
Low Phase Noise Clock Evaluation Module
Contents
1 Features ...................................................................................................................... 1
2 General Description ......................................................................................................... 2
3 Signal Path and Control Circuitry ......................................................................................... 2
4 Getting Started .............................................................................................................. 2
5 Input Clock Selection ....................................................................................................... 2
6 Operating Mode Selection ................................................................................................. 3
7 Output Buffer Termination ................................................................................................. 5
8 Schematic .................................................................................................................... 7
1 Features
• Easy-to-use evaluation module to generate low
phase noise clocks
• Easy device setup
• Rapid configuration
• Control pins configurable through jumpers
• Requires 3.3-V power supply
• Single-ended or crystal input clock reference
• Termination available for LVPECL, LVDS, and
LVCMOS output clocks
Figure 1. CDCM6100xEVM Evaluation Board
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SCAU027B–March 2009–Revised March 2011 Low Phase Noise Clock Evaluation Module
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