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User's Guide
SCAU044–July 2010
Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With
Divider EVM
This user's guide describes how to use the CDCLVD1213 evaluation module (EVM) and provides users
with guidelines to build their own systems. The EVM schematics and bill of materials are included.
Figure 1. CDCLVD1213 Evaluation Board
1 Features
• Easy-to-use evaluation board to fan out low-phase noise clocks
• Easy device setup
• Fast configuration
• Control pin configurable through jumpers
• Board powered at 2.5 V
• Differential input clocks
• Device and EVM support four LVDS outputs
1.1 General Description
The CDCLVD1213 is a high-performance, low-additive jitter clock buffer with divider. The device has one
differential input with internal 140-Ω differential input termination.
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SCAU044–July 2010 Low-Additive Jitter, Four-LVDS-Outputs Clock Buffer With Divider EVM
Copyright © 2010, Texas Instruments Incorporated
