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AM3874, AM3871
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SPRS695C –SEPTEMBER 2011–REVISED DECEMBER 2013
AM387x Sitara™
ARM Processors
Check for Samples: AM3874, AM3871
1 High-Performance System-on-Chip (SoC)
1.1 Features
1
• One 8-/16-/24-Bit Input and One 8-Bit Only
• High-Performance Sitara ARM® Processors
Input Channels
• ARM Cortex-A8 Core
– Two 165-MHz HD Video Display Outputs
– ARMv7 Architecture
• One 16-, 24-, or 30-Bit Output and One 16-
• In-Order, Dual-Issue, Superscalar
or 24-Bit Output
Processor Core
– Composite or S-Video Analog Output
• Neon™ Multimedia Architecture
– Macrovision® Support Available
• Supports Integer and Floating Point
– Digital HDMI 1.3 Transmitter With Integrated
• Jazelle® RCT Execution Environment
PHY
• ARM Cortex-A8 Memory Architecture
– Advanced Video Processing Features Such
– 32KB of Instruction and Data Caches
as Scan, Format, Rate Conversion
– 512KB of L2 Cache
– Three Graphics Layers and Compositors
– 64KB of RAM, 48KB of Boot ROM
• Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
• 128KB of On-Chip Memory Controller (OCMC)
– Supports up to DDR2-800 and DDR3-1066
RAM
– Up to Eight x 8 Devices Total 2GB of Total
• Imaging Subsystem (ISS)
Address Space
– Camera Sensor Connection
– Dynamic Memory Manager (DMM)
• Parallel Connection for Raw (up to 16-Bit)
• Programmable Multi-Zone Memory
and BT.656 or BT.1120 (8- and 16-Bit)
Mapping and Interleaving
– Image Sensor Interface (ISIF) for Handling
• Enables Efficient 2D Block Accesses
Image and Video Data From the Camera
• Supports Tiled Objects in 0°, 90°, 180°, or
Sensor
270° Orientation and Mirroring
– Resizer
• Optimizes Interlaced Accesses
• Resizing Image and Video From 1/16x to
• General-Purpose Memory Controller (GPMC)
8x
– 8- or 16-Bit Multiplexed Address and Data
• Generating Two Different Resizing
Bus
Outputs Concurrently
– 512MB of Address Space Divided Among up
• Media Controller
to 8 Chip Selects
– Controls the HDVPSS and ISS
– Glueless Interface to NOR Flash, NAND
• SGX530 3D Graphics Engine
Flash (BCH/Hamming Error Code Detection),
– Delivers up to 25 MPoly/sec
SRAM and Pseudo-SRAM
– Universal Scalable Shader Engine
– Error Locator Module (ELM) Outside of
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
GPMC to Provide Up to 16-Bit or 512-Byte
OpenVG 1.0, OpenMax API Support
Hardware ECC for NAND
– Advanced Geometry DMA Driven Operation
– Flexible Asynchronous Protocol Control for
– Programmable HQ Image Anti-Aliasing
Interface to FPGA, CPLD, ASICs, and so
Forth
• Endianness
• Enhanced Direct Memory Access (EDMA)
– ARM Instructions/Data – Little Endian
Controller
• HD Video Processing Subsystem (HDVPSS)
– Four Transfer Controllers
– Two 165-MHz, 2-channel HD Video Capture
– 64 Independent DMA Channels and 8
Modules
Independent QDMA Channels
• One 16-/24-Bit Input or Dual 8-Bit SD
• Dual Port Ethernet (10/100/1000 Mbps) With
Input Channels
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2011–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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