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AM3517AZER
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AM3517AZER 产品设计参考 - TI

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AM3517AZER 产品设计参考

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AM3517, AM3505
SPRS550F OCTOBER 2009REVISED JULY 2014
AM3517, AM3505 Sitara™ Processors
1 Device Summary
1.1 Features
1
4 UARTs (One with Infrared Data
AM3517/05 Sitara Processor:
Association [IrDA] and Consumer Infrared
MPU Subsystem
[CIR] Modes)
600-MHz Sitara ARM Cortex
®
-A8 Core
3 Master and Slave High-Speed Inter-
NEON™ SIMD Coprocessor and Vector
Integrated Circuit (I
2
C) Controllers
Floating-Point (FP) Coprocessor
Twelve 32-bit General-Purpose Timers
Memory Interfaces:
One 32-bit Watchdog Timer
166-MHz 16- and 32-Bit mDDR/DDR2
One 32-bit 32-kHz Sync Timer
Interface with 1GB of Total Addressable
Up to 186 General-Purpose I/O (GPIO) Pins
Space
Display Subsystem
Up to 83 MHz General-Purpose Memory
Interface Supporting 16-Bit-Wide Multiplexed
Parallel Digital Output
Address/Data Bus
Up to 24-Bit RGB
64KB of SRAM
Supports Up to 2 LCD Panels
3 Removable Media Interfaces
Support for Remote Frame Buffer Interface
[MMC/SD/SDIO]
(RFBI) LCD Panels
IO Voltage:
Two 10-Bit Digital-to-Analog Converters (DACs)
Supporting
mDDR/DDR2 IOs: 1.8V
Composite NTSC/PAL Video
Other IOs: 1.8V and 3.3V
Luma/Chroma Separate Video (S-Video)
Core Voltage: 1.2V
Rotation of 90, 180, and 270 Degrees
Commercial and Extended Temperature Grade
(operating restrictions apply)
Resize Images From 1/4x to 8x
16-Bit Video Input Port Capable of Capturing
Color Space Converter
HD Video
8-Bit Alpha Blending
HD Resolution Display Subsystem
Video Processing Front End (VPFE) 16-Bit Video
Serial Communication
Input Port
High-End CAN Controller
RAW Data Interface
10/100 Mbit Ethernet MAC
75-MHz Maximum Pixel Clock
USB OTG Subsystem with Standard DP/DM
Supports REC656/CCIR656 Standard
Interface [HS/FS/LS]
Supports YCbCr422 Format (8-Bit or 16-Bit with
Multiport USB Host Subsystem [HS/FS/LS]
Discrete Horizontal and Vertical Sync Signals)
12-Pin ULPI or 6-, 4-, or 3-Pin Serial
Generates Optical Black Clamping Signals
Interface
Built-in Digital Clamping and Black Level
Four Master and Slave Multichannel Serial
Compensation
Port Interface (McSPI) Ports
10-Bit to 8-Bit A-law Compression Hardware
Five Multichannel Buffered Serial Ports
Supports up to 16K Pixels (Image Size) in
(McBSPs)
Horizontal and Vertical Directions
512-Byte Transmit and Receive Buffer
System Direct Memory Access (sDMA) Controller
(McBSP1/3/4/5)
(32 Logical Channels with Configurable Priority)
5-KB Transmit and Receive Buffer
Comprehensive Power, Reset, and Clock
(McBSP2)
Management
SIDETONE Core Support (McBSP2 and
ARM Cortex-A8 Memory Architecture
McBSP3 Only) For Filter, Gain, and Mix
ARMv7 Architecture
Operations
In-Order, Dual-Issue, Superscalar
128-Channel Transmit and Receive Mode
Microprocessor Core
Direct Interface to I2S and PCM Device
ARM NEON Multimedia Architecture
and TDM Buses
Over 2x Performance of ARMv6 SIMD
HDQ/1-Wire Interface
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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AM3517AZER 数据手册 PDF

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