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AD
6
F
E
quipm
e
► Anal
o
► Anal
o
► PC
► USB
► AD6
6
► HSC
-
D
ocume
n
► AD6
6
► Visu
a
► High
► Inter
f
S
o
f
twar
e
► Visu
a
► SPI
C
All docu
m
For any
q
6
649 IF
D
Usin
g
F
igure 1: AD
e
nt Needed
o
g signal so
u
o
g Clock S
o
2.0 port rec
6
49 evaluat
i
-
ADC-EVA
L
n
ts Needed
6
49 Datash
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a
lAnalog C
o
Speed AD
C
f
acing to Hi
g
e
Needed
a
lAnalog
C
ontrolle
r
m
ents and s
o
q
uestions pl
e
Quick
D
iversi
t
g
the FP
6649 Evalua
t
u
rce and an
t
o
urce
ommended
(
i
on boar
d
L
CZ FPGA
e
et
o
nverter Ev
a
C
SPI Contr
o
g
h Speed A
D
o
ftware are
a
e
ase send a
n
Start
G
t
y Recei
v
GA bas
t
ion Board
w
t
i-aliasing fi
l
(
USB 1.1-c
o
Based Data
a
luation Too
l
o
l Software
U
D
Cs via SPI
,
a
vailable at
h
n
email to hi
g
G
uide fo
r
v
er Cu
s
ed Cap
t
EVAL
C
w
ith HSC-A
D
l
te
r
o
mpatible)
Capture Bo
l
User Man
u
U
ser Manua
,
AN-877
h
ttp://www.
g
hspeed.con
v
r
testin
g
s
tomer
E
t
ure Bo
a
C
Z
D
C_EVALC
Z
o
ar
d
u
al, AN-905
a
l, AN-878
analog.com
/
v
erters@ana
l
g
the
E
valuat
i
a
rd HS
C
Z
Data Capt
u
/
fifo.
l
og.co
m
.
i
on Boa
C
-ADC
-
u
re Board
rd
-
