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DS314 (v1.3) June 18, 2009 www.xilinx.com
Product Specification 1
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Summary
The Xilinx® Automotive (XA) Spartan®-3 family of Field-Programmable Gate Arrays meets the needs of high-volume,
cost-sensitive automotive electronic applications. The five-member family offers densities ranging from 50,000 to 1.5 million
system gates, as shown in Ta bl e 1 .
Introduction
XA devices are available in both extended-temperature
Q-grade (–40
°C to +125°C T
J
) and I-grade (–40°C to
+100
°C T
J
) and are qualified to the industry-recognized
AEC-Q100 standard.
The XA Spartan-3 family builds on the success of the earlier
XA Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. These Spartan-3
enhancements, combined with advanced process
technology, deliver more functionality and bandwidth per
dollar than was previously possible, setting new standards
in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of advanced automotive
electronics modules and systems ranging from the latest
driver assistance and infotainment systems to instrument
clusters and gateways.
The Spartan-3 family is a flexible alternative to ASICs,
ASSPs, and microcontrollers. FPGAs avoid the high initial
NREs, the lengthy development cycles, and problems with
obsolescence. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement
necessary.
Features
• AEC-Q100 device qualification and full PPAP
documentation support available in both extended
temperature Q-grade and I-grade
• Guaranteed to meet full electrical specification over the
T
J
= –40°C to +125°C temperature range
• Revolutionary 90-nanometer process technology
• Low cost, high-performance logic solution for
high-volume, automotive applications
♦ Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
• SelectIO™ interface signaling
♦ Up to 487 I/O pins
♦ 622 Mb/s data transfer rate per I/O
♦ Eighteen single-ended signal standards
♦ Eight differential signal standards including LVDS
♦ Termination by Digitally Controlled Impedance
♦ Signal swing ranging from 1.14V to 3.45V
♦ Double Data Rate (DDR) support
• Logic resources
♦ Abundant logic cells with shift register capability
♦ Wide multiplexers
0<BL Blue>
XA Spartan-3 Automotive FPGA Family:
Introduction and Ordering Information
DS314 (v1.3) June 18, 2009
00
Product Specification
R
Tabl e 1 : Summary of Spartan-3 FPGA Attributes
Device
System
Gates
Logic
Cells
CLB Array
(One CLB = Four Slices)
Distributed
RAM (bits
1
)
Block RAM
(bits
1
)
Dedicated
Multipliers DCMs
Maximum
User I/O
Maximum
Differential
I/O PairsRows Columns Total CLBs
XA3S50 50K 1,728 16 12 192 12K 72K 4 2 124 56
XA3S200 200K 4,320 24 20 480 30K 216K 12 4 173 76
XA3S400 400K 8,064 32 28 896 56K 288K 16 4 264 116
XA3S1000 1M 17,280 48 40 1,920 120K 432K 24 4 333 149
XA3S1500 1.5M 29,952 64 52
3,328
208K 576K 32 4 487 221
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
