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Application Report
SLUA296A - October 2003 -- Revised April 2010
1
A New Synchronization Circuit for Power Converters
John Bottrill System Power
ABSTRACT
The synchronization of multiple PWM and PFC controllers is desirable for many reasons. The most
common reason is that it keeps all the noise at one particular frequency and makes it easier to filter.
The circuit described changes the slope of the ramp to lock the converter’s switching frequency to an
applied signal by a phase locked loop turning it into a voltage controlled oscillator. Furthermore, this
circuit is suited for PWM controllers that have internal timing capacitors, such as the UCC28510 family
and the UCC38083 family or that have more than one function dependant on the r amp such as
maximum duty cycle limiting.
The circuits takes both the frequency of the converter and the frequency of the synchronization signal
and mixes the two resulting in a pulse width modulated signal that is changing at the beat frequency
of the two signals. This signal is used to increase or decrease the current that is charging the timing
capacitor forcing the frequency of the converter to match the incoming synchronization signal.
This approach results in:
1. Synchronization of converters where the timing capacitor is unavailable and there is no synchronization pin
available.
2. Uniform ramp amplitude from unit to unit therefore stable voltage gain and current compensation.
3. No distortion of the ramp which allows for maximum duty cycle limiting.
1 Introduction
The synchronization of earlier PWM controllers (eg. UC3842) has usually been implemented by applying a pulse
to the timing capacitor at the CT pin that results in the reset of the timing capacitor voltage being forced to occur
earlier in the cycle than would naturally occur. This results in an effective decrease in the ramp amplitude and
affects the gain of the voltage controlled feedback loop. If the ramp is used to limit duty cycle then this too is
thrown off. In addition the converter frequency can only be increased by this method. With many controllers
having frequency tolerances as high as +/-- 20%, to ensure that you can synchronize, you have to set the unit
to run at a frequency such that if the natural frequency of this converter is high, it will still be lower than the
synchronization frequency. The pulse applied to the CT has to be large enough so that if the converter is running
at its lowest frequency it can still be pulled in. This means that the pulse applied must be as high as 50% of the
natural ramp amplitude.
However some newer controllers also provide a dedicated synchronization pin. This too terminates the ramp
waveform early and reduces the effective ramp amplitude. Again the ramp may be reduced in amplitude by as
much as 50%.
Certain newer converter controllers can not be synchronized in the conventional manner due to the inability to
affect the timing capacitor ramp with an externally applied pulse. One of these is the UCC28517 PFC controller.
This controller has neither an external timing capacitor nor a synchronization pin. However, it does have a
buffered ramp output.
