下载
1997 Microchip Technology Inc. DS00554C-page 1
M
INTRODUCTION
This application note describes the software
implementation of I
2
C interface routines for the
PIC16CXXX family of devices. Only the master mode of
I
2
C interface is implemented in this application note.
This implementation is for a single master communica-
tion to multiple slave I
2
C devices.
Some PIC16CXXX devices, such as the PIC16C64 and
PIC16C74, have on-chip hardware which implements
the I
2
C slave interface, while other PIC16CXXX
devices, such as the PIC16C71 and PIC16C84, do not
have the same on-chip hardware.
This application note does not describe the I
2
C Bus
specifications and the user is assumed to have an
understanding of the I
2
C Bus. For detailed information
on the bus, the user is advised to read the I
2
C Bus
Specification document from Philips/Signetics (order
number 98-8080-575). The I
2
C Bus is a two-wire serial
bus with multiple possible masters and multiple possi-
ble slaves connected to each other through two wires.
The two wires consists of a clock line (SCL) and a data
line (SDA) with both lines being bi-directional. Bi-direc-
tional communication is facilitated through the use of
wire and connection (the lines are either active-low or
passive high). The I
2
C Bus protocol also allows collision
detection, clock synchronization and hand-shaking for
multi-master systems. The clock is always generated by
the master, but the slave may hold it low to generate a
wait state.
Author: Amar Palacherla
Microchip Technology Inc.
In most systems the microcontroller is the master and
the external peripheral devices are slaves. In these
cases this application note can be used to attach I
2
C
slaves to the PIC16CXXX (the master) microcontroller.
The multi-master system is not implemented because it
is extremely difficult to meet all the I
2
C Bus timing spec-
ifications using software. For a true slave or multi-mas-
ter system, some interface hardware is necessary (like
START & STOP bit detection).
In addition to the low level single master I
2
C routines, a
collection of high level routines with various message
structures is given. These high level macros/routines
can be used as canned routines to interface to most I
2
C
slave devices. As an example, the test program talks to
two Serial EEPROMs (Microchip’s 24LC04
and 24LC01).
IMPLEMENTATION
Two levels of software routines are provided. The
low-level routines “
i2c_low.asm
” are provided in
Appendix A and the high level routines
“
i2c_high.asm
” are provided in Appendix B.
The messages passed (communicated on the two wire
network) are abbreviated and certain notation is used
to represent Start, Stop and other conditions. These
abbreviations are described in Table 1.
TABLE 1: DESCRIPTION OF ABBREVIATIONS USED
Abbreviations Explanation
S Start Condition
P Stop Condition
SlvAR Slave Address (for read operation)
SlvAW Slave Address (for write operation)
A Acknowledge condition (positive ACK)
N Negative Acknowledge condition (NACK)
D Data byte, D[0] represents byte 0, D[1] represents second byte
AN554
Software Implementation of I
2
C
Bus Master
