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1 Introduction
A common question is, what is the effect of various system
level parameters on performance? This application note uses
three sample benchmarks to explore the performance effects
by varying those parameters.
The configurations tested do not use masters other than one or
both cores. No DMA or other masters operate during the
benchmarks. These results are useful starting points for users
to get a feel on the system parameter effects on MPC5646B/C.
The best benchmark is always your code.
2 Architecture and
optimization opportunities
2.1 Block diagram
The MPC564xB/C block diagram is shown below. For the
benchmarks, memory banks are dedicated to specific cores in
the linker file.
Freescale Semiconductor
Document Number:AN4666
Application Note
Rev 0, 07/2013
Optimizing MPC564xB/C System
Performance Parameters
Effects of varying key system level parameters are
measured using sample benchmarks
by:
Viktor Fellinger and Steve Mihalik
© 2013 Freescale Semiconductor, Inc.
Contents
1 Introduction............................................................1
2 Architecture and optimization
opportunities............................................................1
3 Descriptions of benchmarks used for
measurements.........................................................8
4 Effect of wait states versus frequency...................10
5 Effect of flash BIU line buffer
configuration..........................................................11
6 Effects of crossbar configuration..........................13
7 Effect of Branch Target Buffers when
enabled..................................................................15
8 Effect of Small Data Area.....................................16
9 Effect of crossbar configuration for dual
core........................................................................17
10 Summary...............................................................28
