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Freescale Semiconductor
Data Sheet: Technical Data
© 2011-2012 Freescale Semiconductor, Inc. All rights reserved.
The P4080 QorIQ integrated communication processor
combines eight Power Architecture® processor cores with
high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and mil/aerospace
applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices, while also
greatly simplifying board design.
This chip includes the following function and features:
• Eight e500-mc Power Architecture cores, each with a
backside 128 KB L2 cache with ECC
– Three levels of instructions: user, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet end-points
• A frontside 2 MB L3 Cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os, data
path accelerators, and high and low speed peripheral
interfaces
• Two 10-Gigabit Ethernet (XAUI) controllers
• Eight 1-Gigabit Ethernet controllers
• Two 64-bit DDR2/DDR3 SDRAM memory controllers
with ECC
• Multicore programmable interrupt controller (MPIC)
•Four I
2
C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
• Two serial RapidIO® 1.2 controllers/ports
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interfaces (eSPI)
• High-speed USB controller (USB 2.0)
– Host and device support
– Enhanced host controller interface (EHCI)
– ULPI interface to PHY
• Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Frame manager (FMan) for packet parsing,
classification, and distribution
– Queue manager (QMan) for scheduling, packet
sequencing, and congestion management
– Hardware buffer manager (BMan) for buffer allocation
and de-allocation
– Encryption/decryption (SEC 4.0)
– Regex pattern matching (PME 2.0)
• 1295 FC-PBGA package
Document Number: P4080EC
Rev. 3, 06/2012
P4080 QorIQ
Integrated Processor
Hardware Specifications
FC-PBGA–1295
37.5 mm x 37.5 mm
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