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Freescale Semiconductor
Data Sheet: Technical Data
© 2010–2013 Freescale Semiconductor, Inc. All rights reserved.
The P2040 QorIQ integrated communication processor
combines four Power Architecture® processor cores with
high performance data path acceleration logic and network
and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and aerospace
applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices, while also
greatly simplifying board design.
This chip includes the following functions and features:
• Four e500mc Power Architecture cores
– Three levels of instructions: User, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet endpoints
• One 1 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os, data
path accelerators, and high and low speed peripheral
interfaces
• Five 1-Gigabit Ethernet controllers
– 2.5 Gbps SGMII interfaces
– RGMII interfaces
• One 64-bit DDR3 and DDR3L SDRAM memory
controller with ECC
• Multicore programmable interrupt controller
•Four I
2
C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
• Two serial RapidIO® controllers/ports (sRIO port)
supporting version 1.3 with features 2.1
• Two serial ATA (SATA 2.0) controllers
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• 2× high-speed USB 2.0 controllers with integrated PHYs
P2040 QorIQ
Integrated Processor
Hardware Specifications
Document Number: P2040EC
Rev. 2, 02/2013
P2040
FCPBGA–780
23 mm x 23 mm
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