March 1996
NDC7002N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features
____________________________________________________________________________________________
Absolute Maximum RatingsT
A
= 25°C unless otherwise noted
Symbol Parameter NDC7002N Units
V
DSS
Drain-Source Voltage 50 V
V
GSS
Gate-Source Voltage - Continuous 20 V
I
D
Drain Current - Continuous (Note 1a) 0.51 A
- Pulsed 1.5
P
D
Maximum Power Dissipation (Note 1a) 0.96 W
(Note 1b)
0.9
(Note 1c)
0.7
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
NDC7002N.SAM
0.51A, 50V, R
DS(ON)
= 2Ω @ V
GS
=10V
High density cell design for low R
DS(ON)
.
Proprietary SuperSOT
TM
-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.
1
5
4
6
3
2
SOT-6 (SuperSOT
TM
-6)
These dual N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. These devices is
particularly suited for low voltage applications requiring a
low current high side switch.
© 1997 Fairchild Semiconductor Corporation
