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Freescale Semiconductor
Application Note
© Freescale Semiconductor, Inc., 2002, 2006. All rights reserved.
This application note describes how to take full advantage of
the MPC8xx caches and MMU features to maximize system
performance. It describes simple ways to measure system
performance.
1 Memory Management Units
The MPC8xx uses one common space to map the program
memory, data memory and peripherals. Therefore, it is
necessary to differentiate various address space areas (pages)
features. The main attributes to control are:
• Protection:
— Read/Write pages (data that can be modified),
read-only pages (program or constant data), No
Access pages (unmapped regions).
— Supervisor/User access pages. Some memory
regions must be accessed only in supervisor
mode.
— Guarded pages prevent speculative accesses to
devices that are not well behaved, such as
peripherals, FIFOs, and so on.
Contents
1 Memory Management Units . . . . . . . . . . . . . . . . . . . . .1
1.1 Basic MMU Features . . . . . . . . . . . . . . . . . . . . . . .2
1.2 Translation Disabled Versus Translation Enabled .6
1.3 Static Page Structure Versus Page on Demand . . . .7
2 Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Cache Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3 D-Cache Flush . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4 Caching Permitted and Inhibited Regions . . . . . .16
2.5 Data/Instruction Lock in Caches . . . . . . . . . . . . . .16
2.6 Coding Practices Affecting Performance . . . . . . .17
3 Performance Estimation and Measurement . . . . . . . .19
3.1 Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2 Cache Hit/Miss Ratio . . . . . . . . . . . . . . . . . . . . . .20
3.3 Instructions Per Clock . . . . . . . . . . . . . . . . . . . . . .25
MPC8xx Performance-Driven
Optimization of Caches and MMU
Configuration
Document Number: AN3066
Rev. 1, 01/2006
