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Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: IMX6SDLAEC
Rev. 5, 06/2015
MCIMX6SxAxxxxxB
MCIMX6SxAxxxxxC
MCIMX6UxAxxxxxB
MCIMX6UxAxxxxxC
Package Information
Plastic Package
BGA Case 2240 21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 3
© 2012-2015 Freescale Semiconductor, Inc. All rights reserved.
1 Introduction
The i.MX 6Solo/6DualLite automotive and infotainment
processors represent Freescale Semiconductor’s latest
achievement in integrated multimedia-focused products
offering high-performance processing with a high degree
of functional integration. These processors are designed
considering the needs of the growing automotive
infotainment, telematics, HMI, and display-based cluster
markets.
The processors feature Freescale’s advanced
implementation of single/dual ARM
®
Cortex
®
-A9 core,
which operates at speeds of up to 800 MHz. They
include 2D and 3D graphics processors, 1080p video
processing, and integrated power management. Each
processor provides a 32/64-bit
DDR3/LVDDR3/LPDDR2-800 memory interface and a
number of other interfaces for connecting peripherals,
i.MX 6Solo/6DualLite
Automotive and
Infotainment
Applications Processors
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3 Updated Signal Naming Convention . . . . . . . . . . . .8
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1 Special Signal Considerations . . . . . . . . . . . . . . . .20
3.2 Recommended Connections for Unused Analog
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .22
4.2 Power Supplies Requirements and Restrictions. . .32
4.3 Integrated LDO Voltage Regulator Parameters . . .34
4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .42
4.8 Output Buffer Impedance Parameters . . . . . . . . . .47
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .50
4.10 General-Purpose Media Interface (GPMI) Timing .67
4.11 External Peripheral Interface Parameters. . . . . . . .75
5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .137
5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .137
5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .139
6 Package Information and Contact Assignments . . . . . .140
6.1 Updated Signal Naming Convention . . . . . . . . . .140
6.2 21x21 mm Package Information . . . . . . . . . . . . . .140
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
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