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MCF5253CVM140 应用笔记 - Freescale

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MCF5253CVM140 应用笔记

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© Freescale Semiconductor, Inc., 2008. All rights reserved.
Freescale Semiconductor
Data Sheet: Technical Data
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
Document Number: MCF5253DS
Rev. 4, 07/2008
MCF5253
Package Information
MAPBGA–225
Ordering Information: See Table 1 on page 2
1 Introduction
This document provides an overview of the MCF5253
ColdFire processor and general descriptions of the
MCF5253 features and modules. Also provided are
electrical specifications, pin assignments, and package
diagrams for MCF5253 ColdFire
®
processor. For
functional characteristics, refer to the MCF5253
Reference Manual (MCF5253RM).
The MCF5253 is a general purpose system controller
with over 125 Dhrystone 2.1 MIPS @ 140 MHz
performance. The integrated peripherals and EMAC
allow the MCF5253 to replace both the microcontroller
and the DSP in certain applications. Most peripheral pins
can also be remapped as general purpose I/O pins.
Low power features include flexible PLL (with
power-down mode) with dynamic clock switching, a
hardwired CD ROM decoder, advanced 0.13 µm CMOS
process technology, 1.2 V core power supply, and
on-chip 128K-byte SRAM.
MCF5253 ColdFire
®
Microprocessor Data
Sheet
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Orderable Part Numbers . . . . . . . . . . . . . . 2
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3
2 Functional Description . . . . . . . . . . . . . . . . . . . 4
2.1 Version 2 ColdFire Core . . . . . . . . . . . . . . . 4
2.2 Module Inventory . . . . . . . . . . . . . . . . . . . . 4
3 Signal Description . . . . . . . . . . . . . . . . . . . . . . 6
4 Electrical Specifications . . . . . . . . . . . . . . . . . 11
4.1 SDRAM Bus Timing . . . . . . . . . . . . . . . . . 16
4.2 SPDIF Timing . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Serial Audio Interface Timing . . . . . . . . . . 17
4.4 DDATA/PST/PSTCLK Debug Interface . . 17
4.5 BDM and JTAG Timing . . . . . . . . . . . . . . 18
5 Power Consumption . . . . . . . . . . . . . . . . . . . . 19
6 Package Information and Pinout . . . . . . . . . . 19
6.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . 20
6.2 Package Drawing . . . . . . . . . . . . . . . . . . . 26
7 Product Documentation . . . . . . . . . . . . . . . . . 33
7.1 Revision History . . . . . . . . . . . . . . . . . . . . 33
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