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数据手册 > 时钟,信号,芯片,时钟信号 > Lattice Semiconductor > ISPPAC-CLK5304S-01TN48C 数据手册PDF > ISPPAC-CLK5304S-01TN48C 应用笔记 第 1/7 页
ISPPAC-CLK5304S-01TN48C
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ISPPAC-CLK5304S-01TN48C 应用笔记 - Lattice Semiconductor

  • 制造商:
    Lattice Semiconductor
  • 分类:
    时钟,信号,芯片,时钟信号
  • 封装
    TQFP-48
  • 描述:
    Zero Delay Buffer 4Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48Pin TQFP
更新时间: 2025-06-17 05:19:47 (UTC+8)

ISPPAC-CLK5304S-01TN48C 应用笔记

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1
an6059_01.1
ispPAC-POWR1208P1 Evaluation Board
PAC-POWR1208P1-EV
March 2007 Application Note AN6059
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
The Lattice Semiconductor ispPAC
®
-POWR1208P1 In-System-Programmable Analog Circuit allows designers to
implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a
single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET
drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208P1 provides the
power-supply designer with a rich set of features in a single device.
ISP™ (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to
configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic
functions. All configuration data is stored internally in E
2
CMOS
®
nonvolatile memory. Programming a configuration
is accomplished through an industry-standard JTAG IEEE 1149.1 interface.
PAC-POWR1208P1-EV Evaluation Board
The PAC-POWR1208P1-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the
ispPAC-POWR1208P1 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP
package, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user pro-
totyping. JTAG programming signals can be generated by using an ispDOWNLOAD
®
programming cable con-
nected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the
ispPAC-POWR1208P1 can be easily configured using PAC-Designer
®
software.
Figure 1. PAC-POWR1208P1-EV Evaluation Board

ISPPAC-CLK5304S-01TN48C 数据手册 PDF

ISPPAC-CLK5304S-01TN48C 数据手册
Lattice Semiconductor
56 页, 1233 KB
ISPPAC-CLK5304S-01TN48C 产品设计参考
Lattice Semiconductor
13 页, 2121 KB
ISPPAC-CLK5304S-01TN48C 产品设计图
Lattice Semiconductor
124 页, 14507 KB
ISPPAC-CLK5304S-01TN48C 应用笔记
Lattice Semiconductor
7 页, 508 KB

ISPPACCLK5304S01TN48 数据手册 PDF

ISPPAC-CLK5304S-01TN48C 数据手册
Lattice Semiconductor
Zero Delay Buffer 4Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48Pin TQFP
ISPPAC-CLK5304S-01TN48I 数据手册
Lattice Semiconductor
Zero Delay Buffer 4Out eHSTL/HSTL/LVCMOS/LVTTL/SSTL Single-Ended 48Pin TQFP
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