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EPM2210F324C5N 应用笔记 - Altera

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EPM2210F324C5N 应用笔记

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© August 2009 Altera Corporation MAX II Device Handbook
Section I. MAX II Device Family Data
Sheet
This section provides designers with the data sheet specifications for MAX
®
II devices.
The chapters contain feature definitions of the internal architecture, Joint Test Action
Group (JTAG) and in-system programmability (ISP) information, DC operating
conditions, AC timing parameters, and ordering information for MAX II devices.
This section includes the following chapters:
Chapter 1, Introduction
Chapter 2, MAX II Architecture
Chapter 3, JTAG and In-System Programmability
Chapter 4, Hot Socketing and Power-On Reset in MAX II Devices
Chapter 5, DC and Switching Characteristics
Chapter 6, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the complete handbook.
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EPM2210F324C5 数据手册 PDF

EPM2210F324C5
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CPLD MAX II Family 1700 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 324Pin FBGA
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Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19MM, 1MM PITCH, FBGA-324
EPM2210F324C5N
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Altera
CPLD MAX II Family 1700 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 324Pin FBGA
EPM2210F324C5N
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Intel
Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19MM, 1MM PITCH, LEAD FREE, FBGA-324
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Altera
CPLD MAX II Family 1700 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 324Pin FBGA
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CPLD MAX II Family 1700 Macro Cells 201.1MHz 0.18um Technology 2.5V/3.3V 324-Pin FBGA
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