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DSP56303AG100
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DSP56303AG100 应用笔记 - NXP

  • 制造商:
    NXP
  • 分类:
    DSP,数字信号,处理器
  • 封装
    LQFP-144
  • 描述:
    DSP 24Bit 100MHz 100MIPS 144Pin LQFP Tray
更新时间: 2025-05-02 07:31:08 (UTC+8)

DSP56303AG100 应用笔记

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AN1751/D
Rev. 01, 05/98
DSP563xx Port A Programming
DSP563xx Port A Programming
by Iantha Scheiwe
The DSP56300 expansion port, Port A, allows the DSP
programmer to expand memory space accessible to the DSP
core or to expand memory-mapped I/O. The interface is
straightforward, and external memory is easily and quickly
retrieved through the use of DMA or simple MOVE
commands. This application note describes:
The hardware and software configurations required
to connect the DSP core to external SRAM and
DRAM
Examples of moves to and from external memory
Examples of DMA accesses
Part 1 Configuration
Part 1 of this application note describes system requirements
and the hardware configuration that you must establish
between the DSP and off-chip memory devices prior to
programming. Part 2 describes the programming required to
interface with SRAM and DRAM. The techniques used in
this application note to interface to external devices enable
you to interface to any device that uses Port A. The code in
this document was developed using the DSP56303EVM and
DSP56301ADM boards. You can use other DSP56300
Family EVMs, but the memory maps for each device may
vary. For complete timing information on the connections
between Port A and memory, see the external memory
interface (Port A) chapter in the DSP56300 Family Manual.
1.1 Performance
The speed of memory access through Port A depends largely
on the speed of the memory used in a system. Port A provides
a programmable number of wait states that correspond to the
specifications of the memory used. A minimum of one wait
state is required for external accesses. Any other timing
issues are determined by system constraints and delays.
Contents
Part 1: Configuration............... 1
1.1 Performance.........................1
1.2 System Set-up......................2
1.2.1 DSP56300 to Memory
Connections.........................2
1.2.2 Memory Map.......................4
1.2.2.1 Address Attributes...............5
1.2.2.2 Bus Control..........................7
1.2.2.3 DRAM Control Register .....8
Part 2: Accessing External
Devices........................ 11
2.1 Simple SRAM Access Using
Move Instruction ............... 11
2.1.1 Initialization.......................11
2.1.2 Program .............................12
2.2 Overlapping External Memory
Space with Internal Core
Space .................................13
2.2.1 Initialization.......................14
2.2.2 Program .............................15
2.3 Multiplexed Access Using
DMA..................................15
2.3.1 Address Attribute Register Bit:
BAM - Address Muxing....15
2.3.2 Initialization.......................17
2.3.3 Program ............................. 18
2.4 Access to an 8-bit Peripheral
Using DMA and Packing
Mode..................................18
2.4.1 Address Attribute Register:
BPAC - Packing Mode......19
2.4.2 Initialization.......................19
2.4.3 Program .............................22
2.5 Accessing DRAM and
SRAM Using DMA
Through Port A..................25
2.5.1 Initialization.......................25
2.5.2 Program .............................29
2.6 Troubleshooting.................31
2.7 Conclusions .......................31
2.8 References .........................31
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc
.
..
Freescale Semiconductor
© Freescale Semiconductor, Inc., 2004. All rights reserved.

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