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Keywords:
E1, T1, unframed, CRC4, ESF, D4, BITS
APPLICATION NOTE 6542
REGISTER CONFIGURATION FOR DS26504
Abstract: This application note describes the basic register settings to configure the DS26504 for operation
in various modes. The device supports three modes each for E1 and T1 operation—for E1, the DS26504
supports unframed mode, as well as CRC4 and FAS framing structure modes; for T1, the device supports
unframed mode, as well as D4 and ESF framing structure modes. The DS26504 can also be configured to
operate with the G.703 and 6312kHz synchronization interfaces, as well as the 64kHz composite clock
interface.
Introduction
The DS26504 is a building-integrated timing supply (BITS) clock-recovery element that also functions as a
reduced function set single-chip transceiver. The receiver portion of this device can recover a clock from E1
and T1, the G.703 and 6312kHz synchronization interfaces, and the 64kHz composite clock interface. This
application note describes how to configure DS26504 registers for operating in each these modes.
Table 1. Acronym Definitions
Acronym Description
CRC Cyclic Redundancy Check
ESF Extended Super Frame
FAS Frame Alignment Signal
SF Superframe
Operating Modes
Configuring the MCREG register allows the user to set the DS26504 to operate in the following modes:
E1 Modes
Unframed
CRC4 Framing Structure
FAS Framing Structure
T1 Modes
Unframed
D4 Framing Structure
ESF Framing Structure
G.703 2.048MHz Synchronous Interface Mode
6312kHz Synchronization Interface Mode
64kHz Composite Clock Mode
E1 Mode
