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DS1233-15+
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DS1233-15+ 应用笔记 - Maxim Integrated

  • 制造商:
    Maxim Integrated
  • 分类:
    电源监控,芯片
  • 封装
    TO-92-3
  • 描述:
    Processor Supervisor 4.125V 5V 3Pin TO-92
更新时间: 2025-05-17 18:30:30 (UTC+8)

DS1233-15+ 应用笔记

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Maxim > Design Support > Technical Documents > Application Notes > Microprocessor Supervisor Circuits > APP 51
Keywords: NV SRAM, SRAM, power fail, nonvolatile memory, power failure, nvsram, PF
APPLICATION NOTE 51
How to Save Data During a Power Fail Without
Corrupting It
May 31, 2001
Abstract: The following application note discusses how the DS1233 can be used to save data during a
power failure without corrupting the NV SRAM.
For many memory systems requiring nonvolatile memory, Dallas Semiconductor NV SRAMs offer an
SRAM's ease of implementation coupled with write protection circuitry and a 10 year information storage
capability. NV SRAMs automatically write protect themselves when they detect an out-of-tolerance
condition (usually at 10% of V
CC
), making them a secure receptacle for data to be protected during a
power failure.
One issue that is not addressed by the secure write protection strategy of the NV SRAM is this: what
happens to the data currently being processed during a power failure? If the voltage has fallen to 10% of
V
CC
, time has already run out to perform any system housekeeping functions such as storing off data
and storing the state of the microprocessor. What is required to truly address this need to "save data
before write-protecting memory" is a method to detect an impending power failure well before the power
supply has fallen to 10% of V
CC
so that a microprocessor can perform these housekeeping functions.
One way to accomplish this task is to use a second voltage monitoring device. Dallas Semiconductor
manufactures the DS1233B, a 5V-5% voltage monitor in a 3-pin TO-92 size package. This 5% monitor
drives an active low reset signal, RST-bar, as soon as it detects an out-of-tolerance condition. This
active low signal can be used as an IRQ-bar input to a microprocessor, providing the microprocessor
with an advanced warning that the power supply is falling, and giving it time to service the interrupt
before the system's nonvolatile memory has been write protected. The following diagram illustrates this
concept.
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