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DP83867IRRGZR 应用笔记 - TI

  • 制造商:
    TI
  • 分类:
    接口,芯片
  • 封装
    VQFN-48
  • 描述:
    PHY 10Mbps/100Mbps/1Gbps 1.8V/2.5V/3.3V 48Pin VQFN EP T/R
更新时间: 2025-04-29 16:19:32 (UTC+8)

DP83867IRRGZR 应用笔记

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Application Report
SNLA242October 2015
How to Configure DP83867 SFDs
PatrickO'Farrell
ABSTRACT
The DP83867 can detect a Start of Frame Delimiter (SFD) for transmit and receive packets and output a
pulse via a GPIO that can be used to assess the latency of the link between the DP83867 and a
timestamp capable partner. For real-time systems and systems implementing the IEEE 1588 Precision
Time Protocol (PTP) to timestamp packets for synchronizing devices across the network, the SFD output
provides a more stable, repeatable timestamp reference when compared to measurements made at the
xGMII interface. This application note provides a brief introduction to Start of Frame Delimiters as they
relate to Ethernet packets and describes the necessary configuration required to implement SFDs in an
Ethernet system.
Contents
1 Synchronization in an Ethernet Application .............................................................................. 1
2 Latency in an Ethernet PHY................................................................................................ 2
3 Start of Frame Detection.................................................................................................... 2
4 Start of Frame Detection in the DP83867 ................................................................................ 3
5 Comparison of SFD versus MAC Interface Signal ...................................................................... 4
6 SFD Measurement Results................................................................................................. 5
7 Conclusions................................................................................................................... 6
List of Figures
1 Ethernet SFD Timestamp Point............................................................................................ 2
2 DP83867 SFD Connection Diagram ...................................................................................... 3
3 Comparison of RX_CTRL vs. RX SFD.................................................................................... 4
4 Start of Frame Measurement............................................................................................... 5
5 Start of Frame Measurement (Zoom) ..................................................................................... 6
1 Synchronization in an Ethernet Application
Synchronization of devices in an Ethernet network is important for real-time systems and systems that
implement the IEEE 1588 Precision Time Protocol. A common element in these systems is that packets
are timestamped and these timestamps are then used to synchronize the time across the network.
Sharing the time throughout the system and synchronizing the devices on the network to a common time
is protocol dependent and is typically handled in the upper layers above the Ethernet Physical Layer
device (commonly referred to as a PHY).
Packets can be timestamped in either hardware or in software depending on the accuracy required for the
application. Every component that handles the packets can increase the error of the timestamp by adding
non-deterministic latency.
Timestamping in the Ethernet MAC is a straightforward implementation, but is subject to multiple sources
of variation. Timestamping within the Ethernet PHY provides better accuracy, but is a more complex
implementation. Generating an SFD pulse prior to the MAC interface and timestamping the pulse offers
good accuracy with moderate complexity.
1
SNLA242October 2015 How to Configure DP83867 Start of Frame Detect
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Copyright © 2015, Texas Instruments Incorporated

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