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CY8C29466, CY8C29566
CY8C29666, CY8C29866
PSoC
®
Programmable System-on-Chip™
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-12013 Rev. *N Revised March 31, 2010
1. Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 3.0V to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC
®
Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 16 Digital PSoC Blocks Provide:
• 8- to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full-Duplex UARTs
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ 24/48 MHz with Optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage 50,000 Erase/Write Cy-
cles
❐ 2K Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ 8 standard analog inputs on GPIO, plus 4 additional analog
inputs with restricted routing
❐ Four 40 mA Analog Outputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ I
2
C Slave, Master, and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software
(PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Bytes Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker
DIGITAL SYSTEM
SRAM
256 Bytes
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Global Digital Interconnect
Global Analog Interconnect
PSoC
CORE
CPU Core (M8C)
SROM Flas h 16K
Digital
Block
Array
Multiply
Accum .
Switch
Mod e
Pump
Internal
Voltage
Ref.
Digital
Clocks
POR and LVD
System Resets
Decimator
SYSTEM RESOURCES
ANALOG SYSTEM
Analog
Ref.
An a l o g
Input
Muxi n g
I C
2
Por t 4 Por t 3 Por t 2 Por t 1 Po r t 0
Analog
Dr iv ers
System Bus
An a l o g
Block
Arr ay
Por t 5
2. Logic Block Diagram
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